(1) Field of the Invention
The present invention relates to a semiconductor device and a fabrication method therefor, and, more particularly, to an MIM (Metal Insulator Metal) type capacitor and a fabrication method therefor.
(2) Description of the Related Art
Each of memory cells of a DRAM (Dynamic Random Access Memory) comprises a selection transistor and a capacitor. As the micropatterning of memory cells becomes finer with the advancement of the microfabrication technology, the amount of electric charges stored in a capacitor undesirably becomes smaller. To solve this problem, active studies have been made on three-dimensional fabrication of a capacitor to increase the electrode area and transition of the capacitor structure from the MIS (Metal Insulator Silicon) structure to the MIM structure.
FIG. 1 is a longitudinal cross-sectional view showing a typical conventional MIM type capacitor. FIG. 2 is a longitudinal cross-sectional view showing one example of a memory cell having an MIM type capacitor.
In the memory cell shown in FIG. 2, two selection transistors are formed in active regions defined on the major surface of a silicon substrate 10 by an isolation insulating film 2 and each selection transistor comprises a gate electrode 4 formed on the major surface of the silicon substrate 10 via a gate insulating film 3, and a pair of diffusion layer regions 5 and 6 to be a source region and a drain region. The diffusion layer regions 5 of the individual selection transistors are shared as a single region.
In the selection transistor, a bit line 8 formed on interlayer insulating films 25 and 26 is connected to the mentioned one diffusion layer region 5 via a polysilicon plug 12 penetrating the interlayer insulating film 25 and a metal plug 7. The bit line 8 is covered with an interlayer insulating film 21. A capacitor is constructed by laminating a ruthenium film 41 as a lower electrode, a ruthenium film 61 as an upper electrode and a tantalum oxide film 51 as a capacitive insulating film in a hole provided in an interlayer insulating film 22 formed on the interlayer insulating film 21.
The lower electrode 41 is connected at its bottom to a barrier metal film 32 which is connected to a polysilicon plug 11 via a contact metal film 31. The polysilicon plug 11 is further connected to the diffusion layer region 6 of the transistor via the underlying polysilicon plug 12.
To improve the charge storage capacitance per unit electrode area by reducing the leak current of the tantalum oxide film 51 in the process of fabricating the capacitor, it is necessary to take a step of oxidizing the tantalum oxide film 51. As a side effect of the step, oxygen is diffused in the lower electrode (ruthenium film), thereby oxidizing the interface portion between the lower electrode 41 and the barrier metal film 32. In case where a titanium nitride film is used for the barrier metal film 32, a titanium oxide film is formed at the interface with the lower electrode 41 and leads to increasing the conductive resistance. Further, the volume expansion that also occurs due to the formation of the titanium oxide film brings about a problem of applying stress to the capacitor, thereby increasing the leak current of the capacitor.
One way of suppressing the diffusion of oxygen in the lower electrode is to make the lower electrode thicker. However, increasing the thickness of the lower electrode by CVD normally causes a film of the same thickness to grow on the side wall portion and the bottom portion. The increase in the thickness of the side wall portion causes a side effect of decreasing the inner circumferential length of the electrode to thereby reduce the amount of electric charges stored in the capacitor (FIG. 3).
As one way of reducing the amount of oxygen diffusion in the lower electrode while preventing the side effect, forming only the bottom portion of the lower electrode of a capacitor in a step separate from the step of forming the other portions of the lower electrode is described in Japanese Patent Laid-Open No. 2002-83940. This method has demonstrated an effect to some extent in suppressing the deterioration of the capacitor characteristic originated from the expansion of the volume of the barrier metal film at the bottom portion of the capacitor (FIG. 4).
However, the prior art illustrated in FIG. 4 has a problem that forming only the bottom portion of the hole in a step separate from the formation of the capacitor portion increases the number of required steps. In addition, since the prior art requires one additional step involving the photolithography technique as compared with the example illustrated in FIG. 1, the process margin for layer alignment becomes narrower.